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ECE 495D ASIC Design Laboratory

Lecture Hours: 1. Lab Hours: 3. Credits: 2.

Experimental Course offered: Spring 2002 through Fall 2005

Prerequisites: ECE 264 and ECE 270

Prerequisites by Topic: familiarity with the fundamentals of digital logic design - including combinational logic design, logic minimization, and state machine design; prior programming experience with a structured programming language needed as preparation for learning to write VHDL code.

Corequisites: None.

Catalog Description: Introduction to standard cell design of VLSI digital circuits using VHDL hardware description language. Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis, and testing.

Required Text(s):

  1. VHDL for Logic Synthesis, 2nd Edition, Andrew Rushton, Wiley, ISBN No. 047198325=X.

Recommended Reference(s):

  1. Digital Design Principles and Practices, 3rd Edition, John F. Wakerly, Prentice Hall, 2001, ISBN No. 0-13-055520-7.

Course Outcomes:

A student who successfully fulfills the course requirements will have demonstrated an ability to:

  1. understand and use major syntactic elements of VDHL - entities, architectures, processes, functions, common concurrent statements, and common sequential statements. [3,4;a,k]
  2. design combinational logic in a variety of styles including: schematic, structural VHDL, and behavioral VHDL, as well as demonstrate an awareness of timing and resource usage associated with each approach. [1,3,4;a,c,k]
  3. design common sequential functions: flip-flops, registers, latches, and state-machines. [1,3,4;a,c,k]
  4. create a VDHL test bench and use it to test/verify a sequential VHDL design of moderate complexity. [3,4;b,k]
  5. place, route, and verify timing of a standard cell design. [3,4;b,c,k]
  6. draw, given commented VHDL code of moderate complexity, a corresponding RTL level block diagram. [1,3,4;a,b,k]
  7. use, modify, and create scripts to control the synthesis process. [3;k]
  8. use different design styles, constraints, and optimization options to achieve required synthesis results. [3,4;a,c,e,k]
  9. explain the difference between various ASIC design approaches - standard cell, full custom, and programmable devices. [1;a]
  10. prepare functional and interface requirements for a sequential design project of the student's choosing. [4,6;a,c,e]
  11. create the hierarchical decomposition of a sequential design. [4;a,c,e]
  12. gain experience in the oral presentation of their work to others. [6;g]
  13. work in a team and negotiate the division of labor. [6;d]
  14. gain familiarity with the use and purpose of design reviews. [6;g]
  15. prepare final design documentation sufficient for another engineer to use, test, or enhance the design. [6;g]

Assessment Method for Course Outcomes:

Outcomes x. through xv. Will be demonstrated by means of a final design project to be completed by teams of two or three students. Final projects will be evaluated on a per team basis, but individual participation will also be evaluated.

Lab Outline:

Week(s) Topic(s)
1 Course overview, VHDL synthesis and simulation design flow
2 Combinational logic design - schematic and VHDL
3 Use of test benches, timing constraints, optimization trade-offs
4 Sequential logic functions in VHDL
5 State machine design in VHDL
6-7 System level design in VHDL; Writing ASIC specifications
8-9 ASIC Place and Route; Timing closure
10-11 Advanced VHDL topics
12-13 ASIC and programmable logic implementation technologies (full custom, standard cell, FPGA)
14-15 Current VLSI topics
Final Student presentations and final reports

Engineering Design Content:
            Establishment of Objectives and Criteria
            Synthesis
            Analysis
            Testing
            Evaluation

Engineering Design Consideration(s):
            Economic
            Manufacturability